FIG. 1A is a schematic circuit structure diagram of a conventional constant ON-time (COT) voltage regulator. As depicted in FIG. 1A, the voltage regulator 100 comprises a feedback circuit 111, an error comparator CMP, an ON-time control circuit 113, a driver & power stage 130 and an output filter 150; herein, the error comparator CMP and the ON-time control circuit 113 together construct a constant ON-time control system. In the voltage regulator 100, the error comparator CMP is configured to compare a reference voltage VREF to a feedback value VFB of an output voltage VOUT provided by the feedback circuit 111, and accordingly output an output voltage logic signal COMP based on the comparing result. The ON-time control circuit 113 is configured to generate and output an OFF-time and an ON-time TON according to a transition time of the voltage logic signal COMP. The driver & power stage 130 is configured to determine a time length of an input voltage VIN inputted to the driver & power stage 130 according to the received ON-time TON, thereby control an inductance current IL resulted in the output filter 150 so as to further modulate the output voltage VOUT. FIG. 1B is a schematic circuit diagram of a power stage part 1302 of the driver & power stage 130 depicted in FIG. 1A. As mentioned above, the driver & power stage 130 is configured to generate a pulse width modulation (PWM) signal VPWM (not shown) according to the ON-time TON thereby the ON-time and OFF-time (equal to the interval time length between two consecutive ON-time) of a transistor HS-MOS is accordingly determined by the pulse width modulation signal VPWM. Moreover, it is indicated that the two coupled transistors HS-MOS and LS-MOS are ON alternatively.
The conventional constant ON-time control system as depicted in FIG. 1A has several advantages, such as having a simple circuit design, no need of a compensation circuit and having a quick response; however, the conventional constant ON-time control system also has disadvantages such as having a varying operation frequency manner. Today, many means are developed to make the constant ON-time control systems have a constant operation frequency manner. FIG. 2 is a schematic circuit structure diagram of a conventional constant frequency ON-time regulator 200.
As depicted in FIG. 2, the conventional constant frequency ON-time regulator 200 comprises a feedback circuit 211, an error comparator CMP, a constant frequency ON-time control circuit 213, a driver & power stage 230 and an output filter 250; herein, the error comparator CMP and the constant frequency ON-time control circuit 213 together construct a constant frequency ON-time control system. In the constant frequency ON-time regulator 200, the constant frequency ON-time control circuit 213 is configured to obtain a value (or an approximate value) of the system duty cycle Duty (i.e., the duty cycle of the pulse width modulation signal VPWM depicted in FIG. 1B) of the voltage regulator 200 according to the input voltage VIN and the output voltage VOUT, and accordingly output a corresponding ON-time TON (herein, TON=VOUT/(VIN×FSET0) or Duty×(1/FSET0) or Duty×(1/FSET0)) to the driver & power stage 230 based on a preset frequency setting parameter FSET0. Thereby, the operation frequency of the constant frequency ON-time regulator 200 is approximately modulated at a constant frequency which is corresponding to the preset frequency setting parameter FSET0. In addition, the OFF-time is automatically determined based on the error comparator CMP comparing the reference voltage VREF to the feedback value VFB of the output voltage VOUT.
However, in a practical circuit realization of a constant frequency ON-time regulator there is a limitation of the minimum OFF-time, which means the practical OFF-time cannot drop under a specific minimum OFF-time. Therefore, once the OFF-time, corresponding to the ON-time and generated by the constant frequency ON-time control circuit 213 as depicted in FIG. 2, is needed to be modulated shorter than the minimum OFF-time, the constant frequency ON-time control system will still maintain the OFF-time at a value of the minimum OFF-time, thereby the pulse width modulation signal VPWM, composed by the minimum OFF-time and the ON-time TON generated by the constant frequency ON-time control circuit 213, may result in an over-low output voltage VOUT so as unable to maintain the output voltage VOUT at a preset level.